The present invention relates to a MOS type semiconductor integrated circuit requiring little margin for signal transmission time.
Signal transmission time in semiconductor integrated circuits composed of MOS (metal oxide semiconductor) type transistors is determined by transfer conductance "gm" of the MOS transistors which controls the voltage at nodes in the circuit and stray capacitance "C" of those nodes. Of these two determinants, "gm" can be accurately estimated on the basis of the electrical performance of the transistors. Accurate estimation of the capacitance "C", however, is difficult. Further, the capacitance "C" changes more than the conductance "gm" does when process parameters are changed in their manufacturing stage. This also makes it difficult to estimate, the precise capacitance values.
Difficult estimation of the stray capacitance "C" results in an inexact estimation of the signal transmission time. It is for this reason that the prior circuit of this type must be designed with a relatively large margin for signal transmission time. Simultaneously, however, there have been technical tendencies in this field, such as increasing integration density and shrinkage by scaling down, towards more complicated construction of the semiconductor circuit and increasing operating speed of the circuit. To satisfy these tendencies, large margins in the circuit operating time must be avoided. In particular, the overall operating speed of the integrated circuit is considerably limited when there is such a large margin in operating speed.